The invention is directed to an electronic circuit for the conversion of data.
In telecommunications technology, data must frequently be processed with different objectives. Transformations from one data format into another data format (protocol conversion), address conversions as well as generating and attaching auxiliary information such as check bits to existing data formats are to be cited as typical examples. As a rule, simple processing jobs can be typically classified with regards to transmission means and reception means.
Traditionally, such processing jobs are implemented by simply constructed hardware circuits that are realized as logic circuits on, for example an ASIC. These hardware circuits are distinguished by high data throughput but have a serious disadvantage in that they are respectively designed and fashioned only for specific processing jobs, so that flexible adaptation to modify job descriptions is almost impossible. Modified job descriptions in the conversion of protocols or data formats therefore regularly require a redesign of the hardware circuit.
Architectures with microprocessor circuits, wherein the microprocessor accesses external memories via a data bus, offer a known alternative to pure hardware circuits. Compared to the aforementioned, pure hardware circuits, these microprocessor circuits offer the advantage that they can be flexibly adapted to modify job descriptions by simple modifications of the program code and without modification of their hardware architecture. However, they have the disadvantage that they usually run more slowly compared to the pure hardware circuits and therefore often do not exhibit an adequate data throughput.
It is an object of the present invention to provide an electrical circuit for the conversion of data with an enhanced data throughput that is also flexible for modified job descriptions.
According to a preferred embodiment of the present invention, the object is achieved in that the electronic circuit, which comprises at least one programmable mini-processor, a program and data memory as well as a bus controller, are integrated on an application-specific integrated circuit (ASIC).
As a result of the integration on the ASIC, the access times for the mini-processors to the program and data memory as well as to the bus controller are shortened. In both instances, the accesses ensue without using an external bus, which results in a clear increase in the data throughput. By modifying the program in the program and data memory, the circuit can be very flexibly adapted to modified job descriptions; a possibility for re-employment of the hardware given modified job descriptions is thus assured. By additional adaptation of the bus controller to new, external interfaces, the ASIC can also be employed in other electronic environments (on other assemblies).
In addition to an increase in the data throughput, an integration of the circuit also offers the advantage that the dependability is enhanced compared to a non-integrated structure. Further, the integration is also advantageous because the circuit is relatively simply constructed. The simple structure requires little development outlay since it is simple to realize by multiple employment of a low number of standard components such as, for example, microprocessors, memories or bus controllers. The integration of the circuit is also simplified in that the standard components are usually available to manufacturers of integrated circuits as library elements. Finally, it should also be pointed out that design errors in integrated circuits can often be eliminated by simple software measures, which contributes to an enhanced design reliability and to a shortening of the market introduction for the circuit.
Over and above this, specific embodiments of the present invention exhibit the following advantages.
The arrangement of a plurality of mini-processors in a pipeline architecture on the ASIC effects an additional enhancement of the data throughput of the ASIC due to a decentralized processing of data.
It is also advantageous to connect the mini-processors in the pipeline to one another via buffer memories for mutual data exchange. A time dependency of the series-connected processors is diminished by the buffer memories insofar as the point-in-time of the output of data by a preceding processor need not correlate with the point-in-time of the acceptance of such data by a following processor. In this way, the buffer memories prevent waiting times of those mini-processors in the pipeline that are dependent on an output of the processor that precedes them.
A fashioning of the buffer memories as first in/first out (FIFO) memories is particularly advantageous because these memories need no complicated addressing.
It is likewise advantageous for enhancing the data throughput that the bus controller comprises a data buffer in which data can be intermediately stored for an access to external memories (memory cycle). The data buffer prevents a waiting time of the mini-processor given external memory cycles. In particular, it allows a parallel operation of bus controller and mini-processor. Whereas the bus controller independently sequences all required, external memory accesses using its data buffer, the mini-processor can simultaneously implement the processing jobs assigned to it.
Given the employment of at least two mini-processors and two bus controllers in the circuit, it is recommended to provide a circuit-internal bus between the two bus controllers via which the data can be directly transmitted, that is, without the detour via the buffer memories of the pipeline. The employment of two bus controllers in the circuit allows access to two different external buses. The connection of the two bus controllers via a circuit-internal bus offers the advantage that data can be very quickly transmitted from a first external bus onto a second external bus without having to run through the pipeline of the mini-processors in a time-consuming manner.
In conclusion, it is advantageous for each of the two mini-processors lying closest to the external data buses to be respectively connected to a bus controller in order to increase the data throughput of the circuit.